1. Field of the Invention
The present invention generally relates to methods for forming device structures on a wafer. Certain embodiments relate to a method that includes transferring approximately an inverse of patterned features formed in a positive resist layer on the wafer to a device material on the wafer to form device structures in the device material.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Semiconductor fabrication processes typically involve a number of lithography steps to form various features and multiple levels of a semiconductor device. Lithography involves transferring a pattern to a resist formed on a semiconductor substrate, which may be commonly referred to as a wafer. A reticle, or a mask, is disposed above the resist and may have substantially transparent regions and substantially opaque regions configured in a pattern that is transferred to the resist. As such, substantially opaque regions of the reticle may protect underlying regions of the resist from exposure to an energy source. The resist may, therefore, be patterned by selectively exposing regions of the resist to an energy source such as ultraviolet light, a beam of electrons, or an x-ray source. The patterned resist may then be used to mask underlying layers in subsequent semiconductor fabrication processes such as ion implantation and etch. Therefore, a resist may substantially inhibit an underlying layer such as a dielectric material or the semiconductor substrate from implantation of ions or removal by etch.
Lithography may be performed using two sequential interleaved lithography exposures. There are a number of methods that are currently used to perform such lithography exposures. One method uses negative photoresist to perform the lithography. This method has a number of disadvantages. For example, positive resists are much more developed and much more commonly used. In addition, it is believed that few negative photoresists for 193 nm exposure exist to meet the requirements for the 32 nm International Technology Roadmap for Semiconductors (ITRS) node.
Another method includes etching between the interleaved photolithography patterning steps. However, this method is disadvantageous for a number of reasons. For example, this method doubles the cycle time and the number of process steps performed in the lithography and etch process cells. In particular, the sequence includes exposing and developing a first resist to create a first patterned resist, etching the first pattern in the material stack below the first resist, depositing, exposing and developing a second resist to create a second patterned resist, and etching the second pattern in the material stack below the second resist. This method is also disadvantageous since overlay error between the first patterned resist and the second patterned resist affects the width of the final etched features.
An additional method includes exposing and developing a first resist to create a first patterned resist, then coating over the first patterned resist with a second resist. The method includes alignment of the second reticle to a pattern formed in the first resist, or to another pattern formed on the wafer, or both. The method includes exposing and developing the second resist to create the second patterned resist, then etching both the first patterned resist pattern and the second patterned resist pattern into the material stack to be etched simultaneously. Such methods are disadvantageous since the second patterned resist will have significant non-uniformity due to the topography of the first patterned resist. This non-uniformity may cause larger variations in the width of the features of the second patterned resist after the features are developed in the second resist and therefore after etch.
Accordingly, it may be advantageous to develop methods for forming device structures in which lithography is performed using two sequential interleaved lithography exposures that eliminate one or more of the disadvantages of the methods described above.